[WIP] mb/hp: Add HP ProBook 640 G1

Generate code from autoport. It boots to Arch Linux in a USB disk from
SeaBIOS payload.

This board doesn't have HP Sure Start enabled, so we can use all the
flash regions, and relocate the EC firmware with CB:41393.

Change-Id: I07f433784292e3765bde3736414ff0eae525a046
Signed-off-by: Iru Cai <mytbk920423@gmail.com>

1 files changed, 86 insertions, 0 deletions

diff --git a/src/mainboard/hp/probook_640_g1/devicetree.cb b/src/mainboard/hp/probook_640_g1/devicetree.cb
new file mode 100644
index 0000000000..5804283217
--- /dev/null
+++ b/src/mainboard/hp/probook_640_g1/devicetree.cb
@@ -0,0 +1,86 @@
+chip northbridge/intel/haswell
+	register "ec_present" = "true"
+	register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+	register "gpu_ddi_e_connected" = "1"
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+	register "gpu_panel_power_backlight_off_delay" = "1"
+	register "gpu_panel_power_backlight_on_delay" = "1"
+	register "gpu_panel_power_cycle_delay" = "6"
+	register "gpu_panel_power_down_delay" = "500"
+	register "gpu_panel_power_up_delay" = "2000"
+	register "gpu_pch_backlight_pwm_hz" = "200"
+	device cpu_cluster 0x0 on
+		chip cpu/intel/haswell
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0x0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0x0 on
+		subsystemid 0x103c 0x1993 inherit
+		device pci 00.0 on end # Host bridge
+		device pci 01.0 on end # PCIe Bridge for discrete graphics
+		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 03.0 on end # Mini-HD audio
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "docking_supported" = "1"
+			register "gen1_dec" = "0x007c0201"
+			register "gen2_dec" = "0x000c0101"
+			register "gen4_dec" = "0x000402e9"
+			register "gpi6_routing" = "2"
+			register "sata_ahci" = "1"
+			register "sata_port0_gen3_dtle" = "0x7"
+			# 0(HDD), 1(ODD), 5(M.2)
+			register "sata_port_map" = "0x37"
+			device pci 14.0 on  end # xHCI Controller
+			device pci 16.0 on  end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 on  end # Intel Gigabit Ethernet
+			device pci 1a.0 on  end # USB2 EHCI #2
+			device pci 1b.0 on  end # High Definition Audio
+			device pci 1c.0 on  end # PCIe Port #1
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 off end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 on  end # PCIe Port #7, WLAN
+			device pci 1c.7 on  end # PCIe Port #8, Card Reader
+			device pci 1d.0 on  end # USB2 EHCI #1
+			device pci 1f.0 on      # LPC bridge
+				chip ec/hp/kbc1126
+					register "ec_data_port" = "0x62"
+					register "ec_cmd_port"  = "0x66"
+					register "ec_ctrl_reg"  = "0x81"
+					register "ec_fan_ctrl_value" = "0x5f"
+					device pnp ff.1 off end
+				end
+				chip superio/smsc/lpc47n217
+					device pnp 4e.3 on	# Parallel
+						io  0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 4e.4 on	# COM1
+						io  0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 off end	# COM2
+				end
+			end
+			device pci 1f.2 on  end # SATA Controller (AHCI)
+			device pci 1f.3 on  end # SMBus
+			device pci 1f.5 off end # SATA Controller (Legacy)
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end