diff options
author | Bill XIE <persmule@gmail.com> | 2017-12-16 10:15:18 +0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-12 18:22:54 +0000 |
commit | ee8da1c3ae873a21767d82c88539b34fd9eff10b (patch) | |
tree | a3871374b77ec4782c58ad0c41cb12c132e09ca4 /src/mainboard/hp/revolve_810_g1/devicetree.cb | |
parent | b15fe8e74edda7b21352d4df3c6186d7f59cc108 (diff) | |
download | coreboot-ee8da1c3ae873a21767d82c88539b34fd9eff10b.tar.xz |
mainboard/hp: Add Elitebook Revolve 810 G1
The code is based on autoport and that for 8470p.
Tested:
- CPU i5-3437U
- Slotted DIMM 8GiB
- Soldered RAM 4GiB from Hynix (There may be more models here)
- Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera)
- Mini pci-e on wlan slot
- On board SDHCI connected to pci-e
- USB3 ports
- USB3 hub on dock (connected to USB3 port 1)
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from
SeaBIOS, or Linux payload (Heads)
Not work:
- An "NFC" device connected to LPC
Not implemented yet:
- Detecting the model of Soldered RAM at runtime, and loading
the corresponding SPD datum (3 observed) from CBFS
Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/hp/revolve_810_g1/devicetree.cb')
-rw-r--r-- | src/mainboard/hp/revolve_810_g1/devicetree.cb | 147 |
1 files changed, 147 insertions, 0 deletions
diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb new file mode 100644 index 0000000000..2384e71c2e --- /dev/null +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -0,0 +1,147 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Bill Xie <persmule@gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00000263" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "230" + register "gpu_panel_power_up_delay" = "300" + register "gpu_pch_backlight" = "0x02880288" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x000402e9" + register "gpi6_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x103c 0x18f8 + end + device pci 16.0 off # Management Engine Interface 1 + subsystemid 0x103c 0x18f8 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + subsystemid 0x103c 0x18f8 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x8086 0x18f8 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x18f8 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x18f8 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x18f8 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x103c 0x18f8 + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x103c 0x18f8 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x18f8 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x18f8 + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x70" + device pnp ff.1 off end + end # kbc1126 + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x18f8 + end + device pci 1f.3 off # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x18f8 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x18f8 + end + end +end |