diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-02 00:57:52 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-20 09:02:19 +0000 |
| commit | 42d300533e6388d0c31d700ec5ea29d21e0216cd (patch) | |
| tree | fc4e749f819fa0b0dd563744c4ac1a49d099b5d2 /src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb | |
| parent | ba9e482a365c6397a4eacafb9ca604374797a7ba (diff) | |
| download | coreboot-42d300533e6388d0c31d700ec5ea29d21e0216cd.tar.xz | |
mb/hp/snb_ivb_laptops: Switch to overridetree setup
NOTE: The ME interface was disabled on folio_9470m and revolve_810_g1.
It is assumed that they were ported while the ME was in an abnormal
state (usually due to me_cleaner usage), and that it should be enabled.
In any case, the MEI device is hidden if the ME fails to boot already.
Change-Id: Ibf32a034653946f49f72a2c19c41a4033964ef83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb')
| -rw-r--r-- | src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb new file mode 100644 index 0000000000..4a797584d5 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -0,0 +1,56 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + register "gpu_cpu_backlight" = "0x00000129" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_pch_backlight" = "0x02880288" + device domain 0x0 on + subsystemid 0x103c 0x162a inherit + + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # mailbox at 0x200/0x201 and PM1 at 0x220 + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen3_dec" = "0x00fcfe01" + register "gen4_dec" = "0x007c0281" + register "gpi6_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" + register "sata_port_map" = "0x21" + + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, ExpressCard + device pci 1c.2 on end # PCIe Port #3, SD/MMC + device pci 1c.3 on end # WLAN + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7, WWAN + device pci 1c.7 off end # PCIe Port #8 + device pci 1f.0 on # LPC bridge + chip ec/hp/kbc1126 + register "ec_data_port" = "0x60" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" + register "ec_fan_ctrl_value" = "0x4d" + device pnp ff.1 off end + end + end + end + end +end |