Simplify a few code chunks, fix whitespace and indentation.

Also, remove some less useful comments, some dead code / unused functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 23 insertions, 44 deletions

diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index bce716cb1a..5352ccc48c 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -27,13 +27,13 @@
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
-      /* Set the memreset low */
-      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
-      /* Ensure the BIOS has control of the memory lines */
-      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+      /* Set the memreset low. */
+      outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+      /* Ensure the BIOS has control of the memory lines. */
+      outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
    } else {
-      /* Ensure the CPU has controll of the memory lines */
-      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+      /* Ensure the CPU has control of the memory lines. */
+      outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
    }
 }
 
@@ -41,8 +41,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
    if (is_cpu_pre_c0()) {
       udelay(800);
-      /* Set memreset_high */
-      outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+      /* Set memreset high. */
+      outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
       udelay(90);
    }
 }
@@ -97,37 +97,29 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-			//first node
-			RC0|DIMM0, RC0|DIMM2, 0, 0,
-			RC0|DIMM1, RC0|DIMM3, 0, 0,
+		//first node
+		RC0|DIMM0, RC0|DIMM2, 0, 0,
+		RC0|DIMM1, RC0|DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-			//second node
-			RC1|DIMM0, RC1|DIMM2, 0, 0,
-			RC1|DIMM1, RC1|DIMM3, 0, 0,
+		//second node
+		RC1|DIMM0, RC1|DIMM2, 0, 0,
+		RC1|DIMM1, RC1|DIMM3, 0, 0,
 #endif
 	};
 
         int needs_reset;
-        unsigned bsp_apicid = 0;
-
+        unsigned bsp_apicid = 0, nodes;
         struct mem_controller ctrl[8];
-        unsigned nodes;
 
         if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
-
 		enumerate_ht_chain();
-
-		/* Setup the amd8111 */
 		amd8111_enable_rom();
         }
 
-        if (bist == 0) {
+        if (bist == 0)
                 bsp_apicid = init_cpus(cpu_init_detectedx);
-        }
-
-//	post_code(0x32);
 
  	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index ce6fd54f8f..ff16b3f8bb 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -59,9 +59,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
@@ -133,7 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		// first node
 		DIMM0, DIMM2, 0, 0,
 		DIMM1, DIMM3, 0, 0,
-
 		// second node
 		DIMM4, DIMM6, 0, 0,
 		DIMM5, DIMM7, 0, 0,
@@ -141,24 +138,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
 	int needs_reset;
 	unsigned bsp_apicid = 0;
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
-
 		enumerate_ht_chain();
 		bcm5785_enable_rom();
 		bcm5785_enable_lpc();
-		//enable RTC
-		pc87417_enable_dev(RTC_DEV);
+		pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 	}
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
 
 	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index d629a7743d..f167b925ac 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -100,30 +100,24 @@ static const u8 spd_addr[] = {
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo =  (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
-	u32 bsp_apicid = 0;
-	u32 val;
+	u32 bsp_apicid = 0, val;
 	msr_t msr;
  
 	if (!cpu_init_detectedx && boot_cpu()) {
-	    /* Nothing special needs to be done to find bus 0 */
+		/* Nothing special needs to be done to find bus 0 */
 		/* Allow the HT devices to be found */
 		/* mov bsp to bus 0xff when > 8 nodes */
 		set_bsp_node_CHtExtNodeCfgEn();
 		enumerate_ht_chain();
-
-		/* Setup the rom access for 4M */
 		bcm5785_enable_rom();
 		bcm5785_enable_lpc();
-		//enable RTC
-		pc87417_enable_dev(RTC_DEV);
+		pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 	}
 
 	post_code(0x30);
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
 
 	pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);