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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:42:04 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-12 19:28:33 +0000 |
| commit | af258cc1791b5c46fcb13d41128cc99043a435be (patch) | |
| tree | 3c143244682d60fed4172086832ae9e4ad66fd76 /src/mainboard/hp | |
| parent | cbbfb702f693c1bbaf83a9d3d8a3c0caabda1814 (diff) | |
| download | coreboot-af258cc1791b5c46fcb13d41128cc99043a435be.tar.xz | |
mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/abm/romstage.c | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 079bd7b786..5092e1772f 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/pci_ops.h> #include <northbridge/amd/agesa/state_machine.h> @@ -26,7 +27,7 @@ void board_BeforeAgesa(struct sysinfo *cb) { - u32 reg32; + u32 t32; /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -37,32 +38,21 @@ void board_BeforeAgesa(struct sysinfo *cb) * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - + pm_io_write8(0xd2, 0); /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x01, 0xcd7); + pm_io_write8(0x24, 1); /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ - reg32 = misc_read32(0x28); - reg32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] - reg32 |= 0x00010000; // Set bit 16 for 25MHz - misc_write32(0x28, reg32); + t32 = misc_read32(0x28); + t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + t32 |= 0x00010000; // Set bit 16 for 25MHz + misc_write(0x28, t32); /* Enable Auxiliary OSCOUT1/OSCOUT2 */ - reg32 = misc_read32(0x40; - reg32 &= 0xffffff7b; // clear 2, 7 - misc_write32(0x40, reg32); + t32 = misc_write32(0x40, misc_read32(0x40) & 0xffffff7b); nct5104d_enable_uartd(SERIAL_DEV); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } - -#if 0 - /* Was before copy_and_run. */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -#endif |