diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-20 23:34:54 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-26 11:32:13 +0000 |
| commit | 66ee42daba635a0748262092b28a3ee87bbfd573 (patch) | |
| tree | 2bd3dc4ce21bfd183c66681d908fd1cd392288ff /src/mainboard/hp | |
| parent | 927f6ae84a7b59b630250a7e559aac1eb05ae2f5 (diff) | |
| download | coreboot-66ee42daba635a0748262092b28a3ee87bbfd573.tar.xz | |
mb/*/*/buildOpts.c: Clean up whitespace
Drop multiple blank lines and use one space inside C-style comments.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/abm/buildOpts.c | 8 | ||||
| -rw-r--r-- | src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 16 |
2 files changed, 9 insertions, 15 deletions
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 05ed0147aa..e3c68a7312 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -33,7 +33,6 @@ #define INSTALL_AM3_SOCKET_SUPPORT FALSE #define INSTALL_FM2_SOCKET_SUPPORT FALSE - #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT @@ -156,7 +155,7 @@ #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' #define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -218,8 +217,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList - -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" #include "cpuFamilyTranslation.h" @@ -254,7 +252,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = //#define DDR2400_FREQUENCY 1200 ///< DDR 2400 //#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency // -///* QUANDRANK_TYPE*/ +///* QUANDRANK_TYPE */ //#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM //#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM // diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index c46ba74f82..dc08a32ab9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -9,15 +9,13 @@ * build option selections desired for that platform. * * For Information about this file, see @ref platforminstall. - * */ #include "mainboard.h" - #include <vendorcode/amd/agesa/f15tn/AGESA.h> -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> @@ -29,14 +27,13 @@ #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> - -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -157,7 +154,7 @@ #if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */ #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif @@ -169,7 +166,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* @@ -253,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define DDR2400_FREQUENCY 1200 ///< DDR 2400 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency -/* QUANDRANK_TYPE*/ +/* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM @@ -339,7 +336,6 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0]) - /* These definitions could be moved to a common Hudson header, should we decide * to provide our own, saner SCI mapping function */ |