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authorPatrick Georgi <patrick.georgi@secunet.com>2012-11-20 11:53:47 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-27 23:51:52 +0100
commite135ac5a7ea69b6edcb89345019212f5de412b1e (patch)
tree408611a9f2846867f9731af53b1f08dd32eb6851 /src/mainboard/hp
parentbdc1816b2379bdf569ac6746172bba41e1307917 (diff)
downloadcoreboot-e135ac5a7ea69b6edcb89345019212f5de412b1e.tar.xz
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/hp')
-rw-r--r--src/mainboard/hp/dl145_g1/romstage.c2
-rw-r--r--src/mainboard/hp/dl145_g3/romstage.c1
-rw-r--r--src/mainboard/hp/dl165_g6_fam10/romstage.c1
3 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index a75d5e14fa..97e1e30603 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -8,10 +8,10 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
+#include <delay.h>
#include "northbridge/amd/amdk8/amdk8.h"
#include "southbridge/amd/amd8111/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/early_serial.c"
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 872a3377fb..7decb72a71 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -42,7 +42,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 8235f9c308..443fa4e87b 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -44,7 +44,6 @@
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
#include <spd.h>
-#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"