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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-28 11:50:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-27 10:18:28 +0200 |
| commit | fb2f667da2091ce2194274f95c2d5db024d46e63 (patch) | |
| tree | 5c9c72faf4d1279a5c6b64ca2ae8a1a879ac84aa /src/mainboard/hp | |
| parent | c0f7a1b7d12062595f01442989e4eac2869e5b7a (diff) | |
| download | coreboot-fb2f667da2091ce2194274f95c2d5db024d46e63.tar.xz | |
nb/amd/amdk8: Link raminit_f.c
For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/dl145_g1/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/hp/dl145_g3/romstage.c | 9 |
2 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 46831322e8..5420df13ef 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -16,7 +16,7 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> @@ -39,7 +39,7 @@ static void memreset_setup(void) } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -51,7 +51,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl) #define SMBUS_HUB 0x18 -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { int ret,i; unsigned device=(ctrl->channel0[0])>>8; @@ -76,7 +76,7 @@ static inline void change_i2c_mux(unsigned device) printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index e7a3b2f36e..6ccaf95d92 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -39,7 +39,7 @@ #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) @@ -47,9 +47,9 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 @@ -58,7 +58,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include <spd.h> #include "cpu/amd/dualcore/dualcore.c" |