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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-11-06 17:11:05 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 17:11:05 +0000 |
| commit | d63085b20ef40caae1c60a7532b5243e1e30b109 (patch) | |
| tree | c732b7666d8082775022592eeddedff81375eeef /src/mainboard/hp | |
| parent | eeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff) | |
| download | coreboot-d63085b20ef40caae1c60a7532b5243e1e30b109.tar.xz | |
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/hp')
| -rw-r--r-- | src/mainboard/hp/e_vectra_p2706t/Config.lb | 1 | ||||
| -rw-r--r-- | src/mainboard/hp/e_vectra_p2706t/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/hp/e_vectra_p2706t/Config.lb b/src/mainboard/hp/e_vectra_p2706t/Config.lb index 0677bbb00c..535c30caa0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Config.lb +++ b/src/mainboard/hp/e_vectra_p2706t/Config.lb @@ -78,7 +78,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index e049c6b46d..a10dee89fc 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end - register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" |