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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-03 12:36:09 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-09 05:23:55 +0000
commit657d68bddc030e38bc19eb4eef07f59b5e5258e4 (patch)
tree90d064a1e09721ae2e9279117ecb71f8ede854eb /src/mainboard/hp
parentdafc78bb8d6bda8bddb029168491365b333ce529 (diff)
downloadcoreboot-657d68bddc030e38bc19eb4eef07f59b5e5258e4.tar.xz
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/hp')
-rw-r--r--src/mainboard/hp/abm/Kconfig1
-rw-r--r--src/mainboard/hp/abm/romstage.c2
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/Kconfig1
-rw-r--r--src/mainboard/hp/pavilion_m6_1035dx/romstage.c1
4 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig
index a179dbe8ca..9e35163180 100644
--- a/src/mainboard/hp/abm/Kconfig
+++ b/src/mainboard/hp/abm/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ select DEFAULT_POST_ON_LPC
select SUPERIO_NUVOTON_NCT5104D
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 2cc8d1bead..d7322c9eee 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -32,8 +32,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80();
-
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
* even though the register is not documented in the Kabini BKDG.
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index 05ea52ff20..144b1138f6 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select DEFAULT_POST_ON_LPC
select EC_COMPAL_ENE932
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
index c05b87a0ec..0395566b74 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c
@@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb)
{
- hudson_lpc_port80();
}