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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 19:12:57 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-14 11:30:09 +0000 |
| commit | 399b6c11efaff64cb86a879dc9047a97538e790f (patch) | |
| tree | ab3a75f247654a8f6c97d75b5dd4d79fe58d3f9e /src/mainboard/ibase/mb899 | |
| parent | 949ff57bcaa3bf7e196b36c90124989a36ba93a5 (diff) | |
| download | coreboot-399b6c11efaff64cb86a879dc9047a97538e790f.tar.xz | |
sb/intel/i82801gx: Add common early code
Remove some of the code duplication on i82801gx.
x4x boards are left untouched for now since that northbridge
also supports i82801jx.
The order of some things has changed:
- on i945 early_ich7_init is now done before the raminit
- enabling the IOAPIC is done before the raminit
Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/ibase/mb899')
| -rw-r--r-- | src/mainboard/ibase/mb899/romstage.c | 36 |
1 files changed, 1 insertions, 35 deletions
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index fd258af554..47e28a8dc1 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -120,42 +120,10 @@ static void rcba_config(void) RCBA16(D28IR) = 0x3201; RCBA16(D27IR) = 0x0146; - /* Enable IOAPIC */ - RCBA8(OIC) = 0x03; - /* Enable PCIe Root Port Clock Gate */ // RCBA32(0x341c) = 0x00000001; } -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { int s3resume = 0; @@ -175,6 +143,7 @@ void mainboard_romstage_entry(void) /* Perform some early chipset initialization required * before RAM initialization can work */ + i82801gx_early_init(); i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); @@ -187,9 +156,6 @@ void mainboard_romstage_entry(void) sdram_initialize(s3resume ? 2 : 0, NULL); - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - /* This should probably go away. Until now it is required * and mainboard specific */ |