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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/ibase/mb899 | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/ibase/mb899')
| -rw-r--r-- | src/mainboard/ibase/mb899/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/ibase/mb899/romstage.c | 18 |
2 files changed, 4 insertions, 17 deletions
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 97f7a7b49d..78743bd453 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -39,6 +39,9 @@ chip northbridge/intel/i945 register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" + register "gen1_dec" = "0x00fc0291" + register "gen4_dec" = "0x00000301" + #device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 3b17e3b634..fd258af554 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,22 +32,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN - | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN - | COMB_LPC_EN); - // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); -} - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -178,7 +162,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - ich7_enable_lpc(); + i82801gx_lpc_setup(); early_superio_config_w83627ehg(); /* Set up the console */ |