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authorUwe Hermann <uwe@hermann-uwe.de>2010-12-05 22:36:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-05 22:36:14 +0000
commit3a4ed157dcd93f845b92fcea272368bdc41d7a11 (patch)
treea38b6e622ebae084de6965d3bc0560f4fbaea5fa /src/mainboard/ibase
parente55eb97f4a6c4ce77d0884aaf1adcb0b29e240bf (diff)
downloadcoreboot-3a4ed157dcd93f845b92fcea272368bdc41d7a11.tar.xz
W83627DHG/W83627EHG fixups for virtual LDNs.
W83627DHG: - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those that don't have their "enable" bit in bit 0 of the 0x30 register). - Fix various I/O masks in the pnp_dev_info[] array as per datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN. W83627EHG: - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was mostly implemented already, though). - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN. Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt for the virtual LDNs. include/device/pnp.h: Add comment that 'function' (which refers to the LDN and should probably be renamed later) has to be at least 16 bits wide. In theory LDNs could use u8, but due to the virtual LDN info being encoded in the "high byte" of 'function' it must be at least u16. asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV. ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial port 1 in this case) to avoid confusion. The global registers manipulated there are accessible from any LDN. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibase')
-rw-r--r--src/mainboard/ibase/mb899/devicetree.cb25
-rw-r--r--src/mainboard/ibase/mb899/romstage.c3
2 files changed, 19 insertions, 9 deletions
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index e9c21a4255..3fbe86314c 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -63,29 +63,38 @@ chip northbridge/intel/i945
irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
end
- device pnp 4e.5 on # Keyboard+Mouse
+ device pnp 4e.5 on # PS/2 keyboard & mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82 # HW accel A20.
end
- device pnp 4e.7 on # GPIO1, GAME, MIDI
- io 0x62 = 0x330
+ device pnp 4e.106 off end # Serial flash interface (SFI)
+ device pnp 4e.007 off end # GPIO 1
+ device pnp 4e.107 off end # Game port
+ device pnp 4e.207 on # MIDI
+ io 0x62 = 0x330
irq 0x70 = 9
end
- device pnp 4e.8 on # GPIO2
- # all default
+ device pnp 4e.307 off end # GPIO 6
+ device pnp 4e.8 off end # WDTO#, PLED
+ device pnp 4e.009 on # GPIO 2
+ # All default
end
- device pnp 4e.9 on # GPIO3/4
- irq 0x30 = 0x03 # does this work?
+ device pnp 4e.109 on # GPIO 3
irq 0xf0 = 0xfb # set inputs/outputs
irq 0xf1 = 0x66
end
+ device pnp 4e.209 on # GPIO 4
+ end
+ device pnp 4e.309 off # GPIO 5
+ end
device pnp 4e.a on # ACPI
+ # TODO: IRQ
end
device pnp 4e.b on # HWM
- io 0x60 = 0x290
+ io 0x60 = 0x290
irq 0x70 = 0
end
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index b9d2f99f62..9902630122 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -38,6 +38,7 @@
#include "southbridge/intel/i82801gx/i82801gx.h"
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+#define DUMMY_DEV PNP_DEV(0x4e, 0)
void enable_smbus(void);
@@ -79,7 +80,7 @@ static void early_superio_config_w83627ehg(void)
{
device_t dev;
- dev=PNP_DEV(0x4e, W83627EHG_SP1);
+ dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCSV