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author | Aaron Durbin <adurbin@chromium.org> | 2016-08-11 17:13:40 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2016-08-19 03:09:49 +0200 |
commit | 67d487e6874b854d5f265e7cc53504ce5319423b (patch) | |
tree | c6634b89aa1dc936e1331476c826982049bdb4ad /src/mainboard/ibase | |
parent | 1ad9f946b6886f08c2cae8503d7efc3f569c1a93 (diff) | |
download | coreboot-67d487e6874b854d5f265e7cc53504ce5319423b.tar.xz |
soc/intel/skylake: make SPI support early stages
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable. Additionally,
include the SPI support code as well as its dependencies in
all the stages.
BUG=chrome-os-partner:56151
Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16196
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/mainboard/ibase')
0 files changed, 0 insertions, 0 deletions