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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-06-17 10:00:28 +0300
committerMartin Roth <martinroth@google.com>2016-06-21 00:49:12 +0200
commit15fa992cc8467b4cbd8ebea62e3e4c947827137e (patch)
tree99e598cc9f4d088a57e04218f2f979a83a6158d6 /src/mainboard/ibase
parent4c3de9c3edd7cb6fabc72337171862930354f0bf (diff)
downloadcoreboot-15fa992cc8467b4cbd8ebea62e3e4c947827137e.tar.xz
intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/ibase')
-rw-r--r--src/mainboard/ibase/mb899/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index b472ba4338..9d2b90ac0d 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -29,6 +29,7 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
#include <halt.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
@@ -217,8 +218,7 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;