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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-05-18 10:33:31 +1000
committerIdwer Vollering <vidwer@gmail.com>2014-05-20 13:47:38 +0200
commit61113de9234f1b933a084c90097ec125fc12f55d (patch)
tree66cbf11365a5fc03ff334a8fd88012e03f2bbd42 /src/mainboard/ibase
parentfb8df3240f5ac80a39b36ca8b5bad291156437a3 (diff)
downloadcoreboot-61113de9234f1b933a084c90097ec125fc12f55d.tar.xz
mainboard/ibase/mb899: Indent devicetree.cb
Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/ibase')
-rw-r--r--src/mainboard/ibase/mb899/devicetree.cb92
1 files changed, 44 insertions, 48 deletions
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb
index 7e5076d8b7..c304908934 100644
--- a/src/mainboard/ibase/mb899/devicetree.cb
+++ b/src/mainboard/ibase/mb899/devicetree.cb
@@ -1,18 +1,17 @@
chip northbridge/intel/i945
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_mFCPGA478
+ device lapic 0 on end
+ end
+ end
- device cpu_cluster 0 on
- chip cpu/intel/socket_mFCPGA478
- device lapic 0 on end
- end
- end
-
- device domain 0 on
- device pci 00.0 on end # host bridge
+ device domain 0 on
+ device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx
+ chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x07"
register "pirqc_routing" = "0x05"
@@ -28,44 +27,42 @@ chip northbridge/intel/i945
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
- register "ide_legacy_combined" = "0x0"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
- register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x1"
- #device pci 1b.0 on end # High Definition Audio
- device pci 1c.0 on end # PCIe
- device pci 1c.1 on end # PCIe
- device pci 1c.2 on end # PCIe
+ #device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.3 on end # USB UHCI
- device pci 1d.7 on end # USB2 EHCI
- device pci 1e.0 on end # PCI bridge
+ device pci 1d.0 on end # USB UHCI
+ device pci 1d.1 on end # USB UHCI
+ device pci 1d.2 on end # USB UHCI
+ device pci 1d.3 on end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
- device pci 1f.0 on # LPC bridge
- chip superio/winbond/w83627ehg
- device pnp 4e.0 off # Floppy
- end
- device pnp 4e.1 off # Parport
+ device pci 1f.0 on # LPC bridge
+ chip superio/winbond/w83627ehg
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.1 off end # Parport
+ device pnp 4e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
end
- device pnp 4e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 4e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
+ device pnp 4e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
- end
+ end
device pnp 4e.5 on # PS/2 keyboard & mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
+ io 0x60 = 0x60
+ io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82 # HW accel A20.
@@ -97,14 +94,13 @@ chip northbridge/intel/i945
io 0x60 = 0x290
irq 0x70 = 0
end
-
- end
-
- end
+ end # chip superio/winbond/w83627ehg
+ end # LPC bridge
device pci 1f.1 on end # IDE
- device pci 1f.2 on end # SATA
- device pci 1f.3 on end # SMBus
- #device pci 1f.4 off end # Realtek ID Codec
- end
- end
-end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ # device pci 1f.4 off end # Realtek ID Codec
+ end # chip southbridge/intel/i82801gx
+
+ end # device domain0
+end # chip northbridge/intel/i945