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authorLi-Ta Lo <ollie@lanl.gov>2004-04-26 17:51:20 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-04-26 17:51:20 +0000
commit5782d273eb79ed32d344273cf344b1580a936183 (patch)
tree37f7e3d68dcab4cc42fb09ca54d5250d910e9763 /src/mainboard/ibm/e325/resourcemap.c
parent1e1a34fdd184a85569b645923b743ec5524fab1d (diff)
downloadcoreboot-5782d273eb79ed32d344273cf344b1580a936183.tar.xz
check in the current code for IBM/E325, can somebody help to fix it ?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibm/e325/resourcemap.c')
-rw-r--r--src/mainboard/ibm/e325/resourcemap.c137
1 files changed, 21 insertions, 116 deletions
diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c
index efeaf6e087..044a5d96f4 100644
--- a/src/mainboard/ibm/e325/resourcemap.c
+++ b/src/mainboard/ibm/e325/resourcemap.c
@@ -1,103 +1,3 @@
-#if 0
-=================== CPU0 ===================
-RAM 0x0(0x3,0x3f0000):
- 0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
- 0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
- 0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
- 0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
- 0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
- 0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
- 0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
- 0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
- 0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
-MMIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
- 0xfec00000:0xfec00000, HT1 CP0, WE:RE
-MMIO 0x5(0xa03,0xb10):
- 0xa0000:0xb0000, HT1 CP0, WE:RE
-MMIO 0x6(0xfed003,0xfed010):
- 0xfed00000:0xfed00000, HT1 CP0, WE:RE
-MMIO 0x7(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
- 0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-CONF 0x0(0xff000103):
- 0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0060):
- 0xff0000:0x00000, HT0 CP6, Dev number compare enable NO WE:NO RE
-CONF 0x2(0xffff0324):
- 0xff0000:0x00000, HT3 CP2, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0204):
- 0xff0000:0x00000, HT2 CP0, Dev number compare enable NO WE:NO RE
-=================== CPU1 ===================
-RAM 0x0(0x3,0x3f0000):
- 0x000:0x3f00(no interleave, bogus), CP0, s: WE
-RAM 0x1(0x400003,0x7f0001):
- 0x4000:0x7f00(no interleave, bogus), CP1, s: WE
-RAM 0x2(0x800000,0x2):
- 0x8000:0x000(no interleave, bogus), CP2, s: NO WE
-RAM 0x3(0x800000,0x3):
- 0x8000:0x000(no interleave, bogus), CP3, s: NO WE
-RAM 0x4(0x800000,0x4):
- 0x8000:0x000(no interleave, bogus), CP4, s: NO WE
-RAM 0x5(0x800000,0x5):
- 0x8000:0x000(no interleave, bogus), CP5, s: NO WE
-RAM 0x6(0x800000,0x6):
- 0x8000:0x000(no interleave, bogus), CP6, s: NO WE
-RAM 0x7(0x800000,0x7):
- 0x8000:0x000(no interleave, bogus), CP7, s: NO WE
-MMIO 0x0(0xfc0003,0xfe2f10):
- 0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
-MMIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-MMIO 0x4(0xfec003,0xfec010):
- 0xfec00000:0xfec00000, HT1 CP0, WE:RE
-MMIO 0x5(0xa03,0xb10):
- 0xa0000:0xb0000, HT1 CP0, WE:RE
-MMIO 0x6(0xfed003,0xfed010):
- 0xfed00000:0xfed00000, HT1 CP0, WE:RE
-MMIO 0x7(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x0(0x33,0x1fff010):
- 0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
-PCIO 0x1(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x2(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-PCIO 0x3(0x0,0x0):
- 0x00000:0x00000, HT0 CP0, NO WE:NO RE
-CONF 0x0(0xff000103):
- 0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
-CONF 0x1(0xffff0200):
- 0xff0000:0x00000, HT2 CP0, NO WE:NO RE
-CONF 0x2(0xffff0370):
- 0xff0000:0x00000, HT3 CP7, Dev number compare enable NO WE:NO RE
-CONF 0x3(0xffff0330):
- 0xff0000:0x00000, HT3 CP3, Dev number compare enable NO WE:NO RE
-#endif
/*
* IBM E325 needs a different resource map
*
@@ -237,22 +137,27 @@ static void setup_ibm_e325_resource_map(void)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfec010,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfec003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xb10,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xa03,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfed010,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfed003,
- PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
+ PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
+ //PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
+ // PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
+ PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
+ //PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
+ PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
+ //PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
+
+ PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
+ PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
+ //PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
+ //PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
+
PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,