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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/ibm/e326
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibm/e326')
-rw-r--r--src/mainboard/ibm/e326/devicetree.cb8
-rw-r--r--src/mainboard/ibm/e326/irq_tables.c2
-rw-r--r--src/mainboard/ibm/e326/resourcemap.c52
-rw-r--r--src/mainboard/ibm/e326/romstage.c4
4 files changed, 33 insertions, 33 deletions
diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb
index a8576968cb..f1759dd81e 100644
--- a/src/mainboard/ibm/e326/devicetree.cb
+++ b/src/mainboard/ibm/e326/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/amdk8/root_complex
end
device pci 1.0 on
chip superio/nsc/pc87366
- device pnp 2e.0 off # Floppy
+ device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
@@ -52,7 +52,7 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.7 off end # GPIO
device pnp 2e.8 off end # ACB
device pnp 2e.9 off end # FSCM
- device pnp 2e.a off end # WDT
+ device pnp 2e.a off end # WDT
end
end
device pci 1.1 on end
@@ -63,12 +63,12 @@ chip northbridge/amd/amdk8/root_complex
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
- end # device pci 18.0
+ end # device pci 18.0
device pci 18.0 on end # LDT2
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
- end
+ end
end
diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c
index a9e8d07166..e537b65ab1 100644
--- a/src/mainboard/ibm/e326/irq_tables.c
+++ b/src/mainboard/ibm/e326/irq_tables.c
@@ -12,7 +12,7 @@
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
/* Each IRQ_SLOT entry consists of:
- * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
+ * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
*/
const struct irq_routing_table intel_irq_routing_table = {
diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c
index a37496879b..98fdcc0ec6 100644
--- a/src/mainboard/ibm/e326/resourcemap.c
+++ b/src/mainboard/ibm/e326/resourcemap.c
@@ -134,7 +134,7 @@ static void setup_ibm_e326_resource_map(void)
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
+ * This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
@@ -143,8 +143,8 @@ static void setup_ibm_e326_resource_map(void)
//PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
// PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
- PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
+ PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
+ PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
//PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
//PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
@@ -153,19 +153,19 @@ static void setup_ibm_e326_resource_map(void)
//PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
//PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
+ PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
//PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
//PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
- PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0xf0, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x8c), 0x48, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0xf0, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x48, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0x80), 0xf0, 0x0,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
@@ -205,7 +205,7 @@ static void setup_ibm_e326_resource_map(void)
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
+ * 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
@@ -213,17 +213,17 @@ static void setup_ibm_e326_resource_map(void)
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
+ * This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
- PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
- PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
- PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
- PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xdc), 0xFE000FC8, 0x1fff010,
+ PCI_ADDR(0, 0x18, 1, 0xd8), 0xFE000FCC, 0x33,
+ PCI_ADDR(0, 0x18, 1, 0xd4), 0xFE000FC8, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xd0), 0xFE000FCC, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xcc), 0xFE000FC8, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xc8), 0xFE000FCC, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xc4), 0xFE000FC8, 0x0,
+ PCI_ADDR(0, 0x18, 1, 0xc0), 0xFE000FCC, 0x0,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
@@ -260,10 +260,10 @@ static void setup_ibm_e326_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
- PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
- PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
- PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
+ PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
+ PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
+ PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
+ PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
};
int max;
max = ARRAY_SIZE(register_values);
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 527db2fa3e..0b38ec78fa 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -1,4 +1,4 @@
-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_ibm_e326_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();