diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2010-11-18 00:11:32 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-11-18 00:11:32 +0000 |
| commit | d28c2986d69141280fce64ac5603b107512f8771 (patch) | |
| tree | de6360ea6339e84020d548d6758dc41b46b67616 /src/mainboard/ibm | |
| parent | 361bd10bcea5db98cfc573987023449c2f59287d (diff) | |
| download | coreboot-d28c2986d69141280fce64ac5603b107512f8771.tar.xz | |
Eliminate SET_NB_CFG_54 option. There was no board that
deselected it, and very likely there won't ever be any
hardware that requires it deselected.
Keep the "selected" code path around, leading to no
functional change.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibm')
| -rw-r--r-- | src/mainboard/ibm/e325/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/ibm/e326/romstage.c | 4 |
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 6ecb219cd3..2ec5a82ddb 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,9 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index b34b4fc93a..22ea09f436 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,9 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" |