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authorStefan Reinauer <stepan@coresystems.de>2008-01-18 15:08:58 +0000
committerStefan Reinauer <stepan@openbios.org>2008-01-18 15:08:58 +0000
commitf8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch)
tree7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/mainboard/iei/nova4899r
parent7e61e45402aba2b90997f4f02ca8266cf65a229a (diff)
downloadcoreboot-f8ee1806ac524bc782c93eccc59ee3c929abddb9.tar.xz
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei/nova4899r')
-rw-r--r--src/mainboard/iei/nova4899r/Config.lb14
-rw-r--r--src/mainboard/iei/nova4899r/Options.lb10
2 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb
index 121e468bd2..3b4094a25f 100644
--- a/src/mainboard/iei/nova4899r/Config.lb
+++ b/src/mainboard/iei/nova4899r/Config.lb
@@ -1,6 +1,6 @@
##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
@@ -12,18 +12,18 @@ end
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
@@ -70,7 +70,7 @@ makerule ./auto.inc
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
@@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
diff --git a/src/mainboard/iei/nova4899r/Options.lb b/src/mainboard/iei/nova4899r/Options.lb
index 771a40b379..778cf737fc 100644
--- a/src/mainboard/iei/nova4899r/Options.lb
+++ b/src/mainboard/iei/nova4899r/Options.lb
@@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
@@ -68,7 +68,7 @@ default HAVE_FALLBACK_BOOT=0
default HAVE_MP_TABLE=0
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
default HAVE_HARD_RESET=0
@@ -90,10 +90,10 @@ default IRQ_SLOT_COUNT=7
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
@@ -149,7 +149,7 @@ default TTYS0_BASE=0x3f8
default TTYS0_LCS=0x3
##
-### Select the linuxBIOS loglevel
+### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately