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| author | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
| commit | 81725b2effe9269e5079c6043077ba516e72aa82 (patch) | |
| tree | 36d93d3eaa95598bef4c64e6595aa454993cfa5e /src/mainboard/iei/pcisa-lx-800-r10 | |
| parent | 5c72a8752bb5ce1c3b1bfb77c08039c71c2113ef (diff) | |
| download | coreboot-81725b2effe9269e5079c6043077ba516e72aa82.tar.xz | |
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei/pcisa-lx-800-r10')
0 files changed, 0 insertions, 0 deletions