diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-13 19:06:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-26 21:33:31 +0200 |
| commit | 7dc2864be7fcc342bab0c167997803f5faf147a1 (patch) | |
| tree | bf94e8694da70ef352eca13a04945e0ddc7c5e70 /src/mainboard/iei/pm-lx-800-r11 | |
| parent | 1b3207ee617c24fd283e654359c20c88d95a69c8 (diff) | |
| download | coreboot-7dc2864be7fcc342bab0c167997803f5faf147a1.tar.xz | |
amd/lx: Move configuration from source to Kconfig
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/iei/pm-lx-800-r11')
| -rw-r--r-- | src/mainboard/iei/pm-lx-800-r11/Kconfig | 19 | ||||
| -rw-r--r-- | src/mainboard/iei/pm-lx-800-r11/romstage.c | 12 |
2 files changed, 6 insertions, 25 deletions
diff --git a/src/mainboard/iei/pm-lx-800-r11/Kconfig b/src/mainboard/iei/pm-lx-800-r11/Kconfig index a897106e68..e443c6c8d6 100644 --- a/src/mainboard/iei/pm-lx-800-r11/Kconfig +++ b/src/mainboard/iei/pm-lx-800-r11/Kconfig @@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS select PIRQ_ROUTE select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_FORCE_ENABLE + select PLL_MANUAL_CONFIG + select CORE_GLIU_500_266 config MAINBOARD_DIR string @@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT int default 7 -choice - prompt "Core/GLIU Frequency" - default CORE_GLIU_500_266 - -config CORE_GLIU_500_266 - bool "500MHz / 266MHz" - -config CORE_GLIU_500_333 - bool "500MHz / 333MHz" - -config CORE_GLIU_500_400 - bool "500MHz / 400MHz" - -endchoice +config PLLMSRlo + hex + default 0x07de0000 endif # BOARD_IEI_PM_LX_800_R11 diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index f7566221db..2992f53c12 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#if CONFIG_CORE_GLIU_500_400 -# define PLLMSRhi 0x0000059c -#elif CONFIG_CORE_GLIU_500_333 -# define PLLMSRhi 0x0000049c -#else -# define PLLMSRhi 0x0000039c -#endif - -#define PLLMSRlo 0x07de000 - #include <northbridge/amd/lx/raminit.h> #include <northbridge/amd/lx/pll_reset.c> #include <northbridge/amd/lx/raminit.c> @@ -80,7 +70,7 @@ void main(unsigned long bist) report_bist_failure(bist); - pll_reset(1); + pll_reset(); cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); |