diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2010-11-20 10:31:00 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-11-20 10:31:00 +0000 |
| commit | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (patch) | |
| tree | 325b7b6abc1d4514d52ad1f726d9be4fa00d0454 /src/mainboard/iei | |
| parent | 622824cadbbbe003bc3e8c97694d2cf6bae0de9b (diff) | |
| download | coreboot-9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a.tar.xz | |
Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).
abuild tested.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei')
| -rw-r--r-- | src/mainboard/iei/kino-780am2-fam10/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 4 |
2 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 6656977bd4..e92f29d26c 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -87,17 +87,13 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> //#include "spd_addr.h" #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index e3351f1294..8412e33170 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -50,9 +51,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) /* Hold Count - how long we will sit in reset */ #define PLLMSRlo 0x00DE6000 -#define DIMM0 0xA0 -#define DIMM1 0xA2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" |