Drop excessive whitespace randomly sprinkled in romstage.c files.

Also drop some dead or useless code snippets.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 3 insertions, 19 deletions

diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c
index 3be347ccf0..96e027872a 100644
--- a/src/mainboard/iei/juki-511p/romstage.c
+++ b/src/mainboard/iei/juki-511p/romstage.c
@@ -30,11 +30,10 @@
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
 #include "cpu/x86/bist.h"
 #include "pc80/udelay_io.c"
+#include "northbridge/amd/gx1/raminit.c"
 
 #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
 
-#include "northbridge/amd/gx1/raminit.c"
-
 static void main(unsigned long bist)
 {
 	/* Initialize the serial console. */
@@ -57,4 +56,3 @@ static void main(unsigned long bist)
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
-
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index de213534f8..eb88647384 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -41,22 +41,16 @@
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #include <lib.h>
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
-
 #include <console/loglevel.h>
 #include "cpu/x86/bist.h"
-
 static int smbus_read_byte(u32 device, u32 address);
-
 #include "superio/fintek/f71859/f71859_early_serial.c"
 #include <usbdebug.h>
-
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include <cpu/amd/mtrr.h>
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
-
 #include "southbridge/amd/rs780/rs780_early_setup.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
@@ -73,18 +67,14 @@ static int spd_read_byte(u32 device, u32 address)
 }
 
 #include "northbridge/amd/amdfam10/amdfam10.h"
-
 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
-
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include <spd.h>
@@ -250,4 +240,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }
-
diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c
index c44ee1a3d2..72f35aae3f 100644
--- a/src/mainboard/iei/nova4899r/romstage.c
+++ b/src/mainboard/iei/nova4899r/romstage.c
@@ -52,4 +52,3 @@ static void main(unsigned long bist)
 	/* Check RAM. */
 	/* ram_check(0x00000000, 640 * 1024); */
 }
-
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
index 4a10c04afc..e889eed09c 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
@@ -31,13 +31,12 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 #include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
 static inline int spd_read_byte(unsigned int device, unsigned int address)
 {
 	return smbus_read_byte(device, address);
@@ -99,4 +98,3 @@ void main(unsigned long bist)
 	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
 	return;
 }
-