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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-12-07 20:48:09 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-03-15 06:16:50 +0000
commit8dffc38f6e8ff4d1f7e26b261bfd6d7fda6be173 (patch)
tree2ef659457ebcd896f534f24a19580afca783123b /src/mainboard/intel/adlrvp/mainboard.c
parente82aa2238d48864a5f8937c2193ee9d09cc0c4d0 (diff)
downloadcoreboot-8dffc38f6e8ff4d1f7e26b261bfd6d7fda6be173.tar.xz
mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/mainboard.c')
-rw-r--r--src/mainboard/intel/adlrvp/mainboard.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index fb2557836a..39462040fe 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -3,6 +3,7 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <device/device.h>
+#include <drivers/intel/gma/opregion.h>
#include <ec/ec.h>
#include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -38,3 +39,17 @@ struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
};
+
+const char *mainboard_vbt_filename(void)
+{
+ uint8_t sku_id = get_board_id();
+ switch (sku_id) {
+ case ADL_P_LP5_1:
+ case ADL_P_LP5_2:
+ return "vbt_lp5.bin";
+ case ADL_P_DDR5:
+ return "vbt_ddr5.bin";
+ default:
+ return "vbt.bin";
+ }
+}