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| author | Subrata Banik <subrata.banik@intel.com> | 2021-01-29 19:05:30 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-01-30 14:38:24 +0000 |
| commit | 1d18c8e3c8a45cc84a41f54fc0dd88712191bc68 (patch) | |
| tree | 24ac5f8be1d7f82421de219f4f32a5cc091b2b19 /src/mainboard/intel/adlrvp | |
| parent | 29148b9cd6798c9e3bc57d893040d4dfe2847259 (diff) | |
| download | coreboot-1d18c8e3c8a45cc84a41f54fc0dd88712191bc68.tar.xz | |
mb/intel/adlrvp: Remove unnecessary whitespace
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index c18223ff47..f2a8f3779a 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -90,17 +90,17 @@ chip soc/intel/alderlake register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, }" register "SataPortsDevSlp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, }" # Enable EDP in PortA @@ -115,12 +115,12 @@ chip soc/intel/alderlake register "s0ix_enable" = "1" register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, }" register "SerialIoGSpiMode" = "{ |