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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 18:33:56 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 10:00:36 +0000
commit3e72f87fe72434216fef63bdcb07ecd63ca03ac6 (patch)
tree5c144c86eff6f9f0c3b65853a68cf04d56aa9c17 /src/mainboard/intel/baskingridge
parente8ecabca73eea669abd453462b80eb10ed536ac3 (diff)
downloadcoreboot-3e72f87fe72434216fef63bdcb07ecd63ca03ac6.tar.xz
mb/intel/baskingridge: Factor out common MRC settings
There's no need to redefine common settings. Change-Id: If0cbc147791496bafc85831c1f88d3eb71b63350 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/intel/baskingridge')
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c122
1 files changed, 58 insertions, 64 deletions
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 62684170ca..6bb09a56bc 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -46,70 +46,64 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data mainboard_pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },
- .ec_present = 0,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 0,
- .dimm_channel1_disabled = 0,
- .max_ddr3_freq = 1600,
- .usb2_ports = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
- USB_PORT_FLEX },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
- USB_PORT_DOCK },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
- USB_PORT_FLEX },
- { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
- USB_PORT_FRONT_PANEL },
- },
- .usb3_ports = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; */
- { 1, 0 }, /* P2; */
- { 1, 0 }, /* P3; */
- { 1, 0 }, /* P4; */
- { 1, 0 }, /* P6; */
- { 1, 0 }, /* P6; */
- },
+ pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[1] = 0xa2;
+ pei_data->spd_addresses[2] = 0xa4;
+ pei_data->spd_addresses[3] = 0xa6;
+ pei_data->ec_present = 0;
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ pei_data->dimm_channel0_disabled = 0;
+ pei_data->dimm_channel1_disabled = 0;
+ pei_data->max_ddr3_freq = 1600;
+
+ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
+ USB_PORT_DOCK },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
+ };
+
+ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; */
+ { 1, 0 }, /* P2; */
+ { 1, 0 }, /* P3; */
+ { 1, 0 }, /* P4; */
+ { 1, 0 }, /* P6; */
+ { 1, 0 }, /* P6; */
};
- *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
+ memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
+ memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
}