diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-08 17:00:37 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 23:11:25 +0100 |
| commit | 467f31de92ca2ed9df1530270e9aabdd69fe8f88 (patch) | |
| tree | 61092ad464c81d2f69cc66fc27e2db1ccb2df710 /src/mainboard/intel/baskingridge | |
| parent | 7922b468b51eea58c7238f11b21820b8d3747d6b (diff) | |
| download | coreboot-467f31de92ca2ed9df1530270e9aabdd69fe8f88.tar.xz | |
haswell/lynxpoint: Use new PCH/PM helper functions
This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.
It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.
The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.
This was tested on WTM2. Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode. Instead I verified that
all of the power management and GPIO registers were set to expected
values.
I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.
Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/baskingridge')
| -rw-r--r-- | src/mainboard/intel/baskingridge/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index c74767a74f..fa3f3e7773 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/intel/haswell register "gpi1_routing" = "1" register "gpi14_routing" = "2" register "alt_gp_smi_en" = "0x0000" - register "gpe0_en" = "0x4000" + register "gpe0_en_1" = "0x4000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" |