diff options
author | Martin Roth <gaumless@gmail.com> | 2014-05-12 21:56:27 -0600 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2014-05-30 17:34:22 +0200 |
commit | d75800c7f2476bee243cc22255acb54d6676d4bc (patch) | |
tree | dd6a6bc232018dbdc8aa2e007da89a77ebf9765a /src/mainboard/intel/bayleybay_fsp/acpi/ec.asl | |
parent | 0f5cf5e45b78d2e6a91d978bb86de5a4ff07c4d5 (diff) | |
download | coreboot-d75800c7f2476bee243cc22255acb54d6676d4bc.tar.xz |
intel/bayleybay: Add Intel's Bayley Bay mainboard
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.
This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.
Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts
Board support page will be updated on acceptance.
Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp/acpi/ec.asl')
-rw-r--r-- | src/mainboard/intel/bayleybay_fsp/acpi/ec.asl | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl b/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/intel/bayleybay_fsp/acpi/ec.asl |