diff options
author | Martin Roth <gaumless@gmail.com> | 2014-05-12 21:56:27 -0600 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2014-05-30 17:34:22 +0200 |
commit | d75800c7f2476bee243cc22255acb54d6676d4bc (patch) | |
tree | dd6a6bc232018dbdc8aa2e007da89a77ebf9765a /src/mainboard/intel/bayleybay_fsp/irqroute.h | |
parent | 0f5cf5e45b78d2e6a91d978bb86de5a4ff07c4d5 (diff) | |
download | coreboot-d75800c7f2476bee243cc22255acb54d6676d4bc.tar.xz |
intel/bayleybay: Add Intel's Bayley Bay mainboard
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board
The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.
This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.
Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts
Board support page will be updated on acceptance.
Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp/irqroute.h')
-rw-r--r-- | src/mainboard/intel/bayleybay_fsp/irqroute.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h new file mode 100644 index 0000000000..4a29b20930 --- /dev/null +++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 4), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) |