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author | John Zhao <john.zhao@intel.com> | 2017-10-20 17:44:24 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-24 15:54:14 +0000 |
commit | b8d66bb6fdb86f4dd6f02fd7e2f9a90717cceafe (patch) | |
tree | 9be899fba75af0f6d44b51c2456b30baf92e9434 /src/mainboard/intel/cannonlake_rvp/mainboard.c | |
parent | aa8e5d36b1b8a5ce1574c3562416e8488ebbb8cc (diff) | |
download | coreboot-b8d66bb6fdb86f4dd6f02fd7e2f9a90717cceafe.tar.xz |
mainboard/intel/cannonlake_rvp: Enable variant gpio configuration
This patch refers to variant_gpio_table for board gpio configuration.
Change-Id: If5b4c20ceccb32fc1ab4246482d8fecb491777c4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/mainboard.c')
-rw-r--r-- | src/mainboard/intel/cannonlake_rvp/mainboard.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/mainboard.c b/src/mainboard/intel/cannonlake_rvp/mainboard.c new file mode 100644 index 0000000000..855d368d56 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/gpio.h> + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; |