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author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2018-09-18 22:53:44 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-04 09:47:22 +0000 |
commit | 2488bea1aa596f5f9bf47acdd58a12147bf8e4ac (patch) | |
tree | e7a322715e6e9732685c753cb9a4e61495d51c42 /src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c | |
parent | 742c6fedbd79410df8397960dd33ae48ae0b3b72 (diff) | |
download | coreboot-2488bea1aa596f5f9bf47acdd58a12147bf8e4ac.tar.xz |
mb/intel/cannonlake_rvp: Move FSP param override function to separate file
Move the FSP param initialization function to a separate file,
as being done on the SoC side and remove the empty romstage.c file.
Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c')
-rw-r--r-- | src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c new file mode 100644 index 0000000000..457be7f2c7 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index; + + mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + spd_index = 2; + + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +} |