diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-08 18:16:13 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-26 21:37:14 +0000 |
| commit | c319bab3cd416d85330774f9974b41fcb49075a7 (patch) | |
| tree | 7533dac79d57499e552393695b5c751a2986eb5c /src/mainboard/intel/cannonlake_rvp/spd/spd.h | |
| parent | 735779cc9aa9d6b02fadbdfc0a50fb087cce7731 (diff) | |
| download | coreboot-c319bab3cd416d85330774f9974b41fcb49075a7.tar.xz | |
intel/cannonlake_rvp: Split RVP boards and SPD
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/spd/spd.h')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/spd/spd.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h new file mode 100644 index 0000000000..128eb64a3c --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif |