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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-09-06 12:42:06 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-13 03:09:31 +0000 |
| commit | a17e4e4423f532eb97ddbc0bea58bdc1a8c109ca (patch) | |
| tree | 82041a402ad38e2ee248da00093ce635d2bd2e01 /src/mainboard/intel/cannonlake_rvp | |
| parent | 2b074d90ae0d20f2d3171f2ddc5d0b6c0d3b78b0 (diff) | |
| download | coreboot-a17e4e4423f532eb97ddbc0bea58bdc1a8c109ca.tar.xz | |
mainboard/intel/cannonlake_rvp: Add dummy DSDT table
Add dummy ACPI DSDT table for cannonlake rvp platform.
Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/acpi_tables.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/dsdt.asl | 37 |
3 files changed, 39 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 35afb07718..9d2a5f2279 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_CANNONLAKE + select HAVE_ACPI_TABLES select GENERIC_SPD_BIN config MAINBOARD_DIR diff --git a/src/mainboard/intel/cannonlake_rvp/acpi_tables.c b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c new file mode 100644 index 0000000000..3b44754e30 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c @@ -0,0 +1 @@ +/* Nothing here */ diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl new file mode 100644 index 0000000000..712ea0524a --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + } + + #if IS_ENABLED(CONFIG_CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + #endif +} |