intel/cannonlake_rvp: Clean up GPIO programming

Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4
platform, it is also critical to revisit the GPIO settings as they are
different. Remove unused GPIO setting for old platform, and clean up the
native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set
to GPIO mode is illegal.

TEST=Boot up in chromeos successfully.

Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

1 files changed, 19 insertions, 49 deletions

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
index b69d338323..f50c5b7e85 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
@@ -30,9 +30,7 @@ static const struct pad_config gpio_table[] = {
 	/* A7  : PRIQAB_GSP10_CS1B */
 	PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),
 	/* A8  : CLKRUNB */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
 	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
-#endif
 	/* A9  : CLKOUT_LPC_0_ESPI_CLK */
 	/* A10 : CLKOUT_LPC_1 */
 	/* A11 : PMEB_GSP11_CS1B */
@@ -47,17 +45,17 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_A16, 0, PLTRST),
 	/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
 	/* A18 : ISH_GP_0 */
-	PAD_CFG_NF(GPP_A18, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),
 	/* A19 : ISH_GP_1 */
-	PAD_CFG_NF(GPP_A19, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
 	/* A20 : ISH_GP_2 */
-	PAD_CFG_NF(GPP_A20, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1),
 	/* A21 : ISH_GP_3 */
-	PAD_CFG_NF(GPP_A21, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
 	/* A22 : ISH_GP_4 */
-	PAD_CFG_NF(GPP_A22, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),
 	/* A23 : ISH_GP_5 */
-	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
 
 	/* B0  : CORE_VID_0 */
 	/* B1  : CORE_VID_1 */
@@ -74,18 +72,13 @@ static const struct pad_config gpio_table[] = {
 	/* B9  : SRCCLKREQB_4 */
 	/* B10 : SRCCLKREQB_5 */
 	/* B11 : EXT_PWR_GATEB */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
 	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
-#endif
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)
-	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
-#endif
 	/* B12 : SLP_S0B */
 	/* B13 : PLTRSTB */
 	/* B14 : SPKR */
 	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
 	/* B15 : GSPI0_CS0B */
-	PAD_CFG_NF(GPP_B15, NONE, DEEP, GPIO),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
 	/* B16 : GSPI0_CLK */
 	PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
 	/* B17 : GSPI0_MISO */
@@ -175,17 +168,10 @@ static const struct pad_config gpio_table[] = {
 	/* E3  : CPU_GP_0 */
 	PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
 	/* E4  : SATA_DEVSLP_0 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
-	PAD_CFG_NF(GPP_E4, NONE, DEEP,  NF1),
-#endif
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)
-	PAD_CFG_GPI_SCI_HIGH(GPP_E4, NONE, PLTRST, LEVEL),
-#endif
+	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
 	/* E5  : SATA_DEVSLP_1 */
 	/* E6  : SATA_DEVSLP_2 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
 	PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),
-#endif
 	/* E7  : CPU_GP_1 */
 	PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),
 	/* E8  : SATA_LEDB */
@@ -196,13 +182,8 @@ static const struct pad_config gpio_table[] = {
 	/* E13 : DDSP_HPD_0_DISP_MISC_0 */
 	/* E14 : DDSP_HPD_0_DISP_MISC_1 */
 	/* E15 : DDSP_HPD_0_DISP_MISC_2 */
-	/* E16 : DDSP_HPD_0_DISP_MISC_3 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
-	PAD_CFG_GPO(GPP_E16, 1, DEEP),
-#endif
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)
-	PAD_CFG_GPI_SCI_HIGH(GPP_E16, NONE, DEEP, LEVEL),
-#endif
+	/* E16 : EMMC_EN */
+	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
 	/* E17 : EDP_HPD_DISP_MISC_4 */
 	/* E18 : DDPB_CTRLCLK */
 	/* E19 : DDPB_CTRLDATA */
@@ -212,7 +193,7 @@ static const struct pad_config gpio_table[] = {
 	/* E23 : DDPD_CTRLDATA */
 
 	/* F0  : CNV_GNSS_PA_BLANKING */
-	PAD_CFG_NF(GPP_F0, NONE, DEEP, GPIO),
+	PAD_CFG_GPI(GPP_F0, NONE, PLTRST),
 	/* F1  : CNV_GNSS_FAT */
 	PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),
 	/* F2  : CNV_GNSS_SYSCK */
@@ -228,12 +209,7 @@ static const struct pad_config gpio_table[] = {
 	/* F9  : CNV_MFUART2_TXD */
 	PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),
 	/* F10 : GPP_F_10 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
-	PAD_CFG_GPO(GPP_F10, 1, DEEP),
-#endif
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)
-	PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST),
-#endif
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
 	/* F11 : EMMC_CMD */
 	/* F12 : EMMC_DATA0 */
 	/* F13 : EMMC_DATA1 */
@@ -246,20 +222,18 @@ static const struct pad_config gpio_table[] = {
 	/* F20 : EMMC_RCLK */
 	/* F21 : EMMC_CLK */
 	/* F22 : EMMC_RESETB */
-	/* F23 : EMMC_PRESENT */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
+	/* F23 : BIOS_REC */
 	PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),
-#endif
 	/* G0  : SD3_D2 */
 	/* G1  : SD3_D0_SD4_RCLK_P */
 	/* G2  : SD3_D1_SD4_RCLK_N */
 	/* G3  : SD3_D2 */
 	/* G4  : SD3_D3 */
 	/* G5  : SD3_CDB */
-	PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),
 	/* G6  : SD3_CLK */
 	/* G7  : SD3_WP */
-	PAD_CFG_NF(GPP_G7, DN_20K, DEEP, GPIO),
+	PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
 
 	/* H0  : SSP2_SCLK */
 	/* H1  : SSP2_SFRM */
@@ -283,14 +257,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
 	/* H15 : M2_SKT2_CFG_3 */
 	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
-	/* H16 : DDPF_CTRLCLK */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
-	PAD_CFG_GPO(GPP_H16, 1, DEEP),
-#endif
-	/* H17 : DDPF_CTRLDATA */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
-	PAD_CFG_GPO(GPP_H17, 1, DEEP),
-#endif
+	/* H16 : CAM5_PWR_EN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* H17 : CAM5_FLASH_STROBE */
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),
 	/* H18 : BOOTMPC */
 	/* H19 : TIMESYNC_0 */
 	PAD_CFG_GPO(GPP_H19, 1, PLTRST),