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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2017-09-10 17:35:58 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-14 21:10:57 +0000
commitb2d6902086d6b7058d8d7a31959c1a16264e4092 (patch)
tree4f3faa2081390904af947d72f447a3c14a6db3b4 /src/mainboard/intel/cannonlake_rvp
parentc82e1fbcabe54b4c19d93f4252df93a606dfb075 (diff)
downloadcoreboot-b2d6902086d6b7058d8d7a31959c1a16264e4092.tar.xz
mainboard/intel/cannonlake_rvp-y: Configure USB ports
Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index dad18e7ff7..7f3e7a5f14 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -10,6 +10,24 @@ chip soc/intel/cannonlake
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[9]" = "USB2_PORT_EMPTY"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device