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authorBora Guvendik <bora.guvendik@intel.com>2017-09-05 17:09:30 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-11 18:08:41 +0000
commit0a712c33379799b13215068e4dcbad8272d38ccc (patch)
tree4b59512a448e2e6b91f23504878173cf1d4444a2 /src/mainboard/intel/cannonlake_rvp
parent2d1e0eb8a77ff4eb08b3ccd059d3eee3bef2201d (diff)
downloadcoreboot-0a712c33379799b13215068e4dcbad8272d38ccc.tar.xz
mainboard/intel/cannonlake_rvp: enable eMMC
Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index a3c4c80d14..dad18e7ff7 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -8,6 +8,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
device domain 0 on
device pci 00.0 on end # Host Bridge
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index a3c4c80d14..dad18e7ff7 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -8,6 +8,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
device domain 0 on
device pci 00.0 on end # Host Bridge