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| author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-04-26 21:08:20 +0300 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-30 22:15:31 +0000 |
| commit | 04a2edf689f79ffeb540c3e39e8893e75d5efd7a (patch) | |
| tree | 418ca178d0c4647bc846717d7feeacabffb98030 /src/mainboard/intel/cedarisland_crb/bootblock.c | |
| parent | 98a47ac9b52cad2ec94204e6839e0bb8fdfb30f3 (diff) | |
| download | coreboot-04a2edf689f79ffeb540c3e39e8893e75d5efd7a.tar.xz | |
mb/intel/cedarisland_crb: use common driver to configure GPIO
According to changes in the soc/xeon_sp code [1,2], server motherboards
with Lewisburg PCH can use the soc/intel/common/gpio driver to configure
GPIO controller. This patch adds pads configuration map, which has the
format required by the GPIO driver. The data for this was taken from the
inteltool register dump with vendors firmware. The gpio.h file with pad
configuration was generated automatically using the util/intelp2m [3]:
./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log
[1] https: //review.coreboot.org/c/coreboot/+/39425
[2] https: //review.coreboot.org/c/coreboot/+/39428
[3] https: //review.coreboot.org/c/coreboot/+/35643
Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Diffstat (limited to 'src/mainboard/intel/cedarisland_crb/bootblock.c')
| -rw-r--r-- | src/mainboard/intel/cedarisland_crb/bootblock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index ea82ecc73f..3be0f8bc10 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -10,9 +10,13 @@ #include <soc/pcr_ids.h> #include <superio/aspeed/ast2400/ast2400.h> #include <superio/aspeed/common/aspeed.h> +#include "include/gpio.h" void bootblock_mainboard_early_init(void) { + /* Configure Lewisburg PCH GPIOs */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + /* Enable COM1 only */ pcr_write32(PID_DMI, 0x2770, 0); pcr_write32(PID_DMI, 0x2774, 1); |