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author | Lijian Zhao <lijian.zhao@intel.com> | 2018-08-21 10:50:16 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-16 08:34:50 +0000 |
commit | f349672966fcde4f943c2a5de3c086971aaded44 (patch) | |
tree | bdd54e399cb2ed1c7c3bdd1feb96961cc324ab02 /src/mainboard/intel/coffeelake_rvp/memory.c | |
parent | 6f7db0710281466866604a7cfc7d68df94d82ada (diff) | |
download | coreboot-f349672966fcde4f943c2a5de3c086971aaded44.tar.xz |
mb/intel/coffelake_rvp: Implement mainboard memory information
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform
for easier collabration on newer platform. The setting in memory.c get
from board design itself.
BUG=N/A
TEST=Build and boot up with whiskey lake rvp platform.
Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28257
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp/memory.c')
-rw-r--r-- | src/mainboard/intel/coffeelake_rvp/memory.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c new file mode 100644 index 0000000000..7058be4130 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <compiler.h> +#include <gpio.h> +#include <soc/cnl_memcfg_init.h> + +static const struct cnl_mb_cfg baseboard_memcfg_cfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, + .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Baseboard Rcomp target values. + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Baseboard is an interleaved design */ + .dq_pins_interleaved = 1, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Disable Early Command Training */ + .ect = 0, +}; + +const struct cnl_mb_cfg *__weak variant_memcfg_config(void) +{ + return &baseboard_memcfg_cfg; +} |