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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-07-31 17:23:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-28 09:53:01 +0000 |
| commit | b269f873b0a0d43911adc907a53bbebadc742b78 (patch) | |
| tree | 23e53691cef9dcfd19d63d8128e28638699aae97 /src/mainboard/intel/coffeelake_rvp | |
| parent | 80346d04906261b258e1f7ea737a74beac08b11a (diff) | |
| download | coreboot-b269f873b0a0d43911adc907a53bbebadc742b78.tar.xz | |
soc/intel/cannonlake: Update UPD from device switch
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp')
3 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 8b36785d57..9115fd93f6 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb index 6bd90a55ac..3357140fc1 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 62a6635e0a..34270cd097 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -6,10 +6,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "HeciEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" @@ -30,7 +27,6 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" - register "SataEnable" = "1" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" |