diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2018-09-06 18:15:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-12 12:25:30 +0000 |
| commit | 803cf02801e4681604661bd8f6587fd303042b7a (patch) | |
| tree | 94d6dc8811881e7504454dd0624f097a54e9eedb /src/mainboard/intel/coffeelake_rvp | |
| parent | 15192da7c756eead1e3ccb2d3c7781bf96680925 (diff) | |
| download | coreboot-803cf02801e4681604661bd8f6587fd303042b7a.tar.xz | |
mainboards: Add SMMSTORE region in chromeos configs
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp')
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/chromeos.fmd | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd index cca80ab6a4..65d22c3950 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.fmd @@ -28,7 +28,8 @@ FLASH@0xff000000 0x1000000 { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x700000 0x200000 + SMMSTORE@0x700000 0x40000 + RW_LEGACY(CBFS)@0x740000 0x1c0000 WP_RO@0x900000 0x380000 { RO_VPD@0x0 0x4000 RO_UNUSED@0x4000 0xc000 diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd index be6bfc07b6..bfbd304d36 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd +++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd @@ -28,7 +28,8 @@ FLASH@0xfe000000 0x2000000 { RW_VPD@0x28000 0x2000 RW_NVRAM@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x200000 + SMMSTORE@0x5d0000 0x40000 + RW_LEGACY(CBFS)@0x610000 0x1c0000 WP_RO@0x7d0000 0x430000 { RO_VPD@0x0 0x4000 RO_SECTION@0x4000 0x42c000 { |