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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-04 21:33:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2015-01-06 01:51:42 +0100
commit77757c22b9eede92234d07d65a23fdf4b970c8cf (patch)
tree29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/intel/cougar_canyon2
parentd76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff)
downloadcoreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/intel/cougar_canyon2')
-rw-r--r--src/mainboard/intel/cougar_canyon2/romstage.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index a660df2a25..72832ea4cb 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -35,11 +35,11 @@
#include <reset.h>
#include <superio/smsc/sio1007/chip.h>
#include <fsp_util.h>
-#include "northbridge/intel/fsp_sandybridge/northbridge.h"
-#include "northbridge/intel/fsp_sandybridge/raminit.h"
-#include "southbridge/intel/fsp_bd82x6x/pch.h"
-#include "southbridge/intel/fsp_bd82x6x/gpio.h"
-#include "southbridge/intel/fsp_bd82x6x/me.h"
+#include <northbridge/intel/fsp_sandybridge/northbridge.h>
+#include <northbridge/intel/fsp_sandybridge/raminit.h>
+#include <southbridge/intel/fsp_bd82x6x/pch.h>
+#include <southbridge/intel/fsp_bd82x6x/gpio.h>
+#include <southbridge/intel/fsp_bd82x6x/me.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "gpio.h"