diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-10-25 11:55:26 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-21 12:10:53 +0000 |
| commit | 15209ce39ac510858fea783b9a2dfedee126f502 (patch) | |
| tree | a5d242acbb0750453fe428948dca42b2c6f32e7e /src/mainboard/intel/d510mo/dsdt.asl | |
| parent | 5ba184000b7786bed162e7c8e1ecc03e67017390 (diff) | |
| download | coreboot-15209ce39ac510858fea783b9a2dfedee126f502.tar.xz | |
mb/google/octopus: Update TSR1 threshold settings
Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.
BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards
Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d510mo/dsdt.asl')
0 files changed, 0 insertions, 0 deletions