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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 17:22:00 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:39:47 +0200 |
| commit | 07921540dda79d810d8bfc6be211513c238a0d63 (patch) | |
| tree | 6395b9d31d8030480004a6af8f1afc12394f678f /src/mainboard/intel/d810e2cb | |
| parent | 633c57d1d1ab3b2241fd259e12423054527ee000 (diff) | |
| download | coreboot-07921540dda79d810d8bfc6be211513c238a0d63.tar.xz | |
intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/d810e2cb')
| -rw-r--r-- | src/mainboard/intel/d810e2cb/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 934cb173a1..5bcee0c544 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -23,14 +23,14 @@ #include <southbridge/intel/i82801bx/i82801bx.h> #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" #include <lib.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); |