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| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-14 08:35:11 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-08-15 03:44:46 +0200 |
| commit | a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e (patch) | |
| tree | a0233b3d5b638eb05bf5a4d57ee64e73187da677 /src/mainboard/intel/d810e2cb | |
| parent | b7f1bfcf289f218f05dfb17561a5b868eea65b92 (diff) | |
| download | coreboot-a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e.tar.xz | |
intel/cpu: rename car.h to romstage.h
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.
Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d810e2cb')
| -rw-r--r-- | src/mainboard/intel/d810e2cb/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 982060c3b3..8b74b17d9f 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -35,7 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -#include <cpu/intel/car.h> +#include <cpu/intel/romstage.h> void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ |