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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-07 15:33:46 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-08 14:28:56 +0000 |
| commit | 79a7ad6dda8a5a4272b6a59cef750af2f2585dc2 (patch) | |
| tree | 72df0570b29aa46c8e7e2d07816df3a7531213c5 /src/mainboard/intel/d945gclf/cstates.c | |
| parent | d25109905aa46fce557d2905a43c347ca5be1aa0 (diff) | |
| download | coreboot-79a7ad6dda8a5a4272b6a59cef750af2f2585dc2.tar.xz | |
mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6
The southbridge has the function disable bits for port 5 and 6
strapped RO to 1 (disable).
Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf/cstates.c')
0 files changed, 0 insertions, 0 deletions