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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2016-12-29 22:46:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-12 11:39:07 +0000 |
| commit | 81dd52b7eb663c6098de5d8c7c56ed572c91b539 (patch) | |
| tree | 02f56645bcc26ce8e861481bb5bb11f290729c20 /src/mainboard/intel/d945gclf/devicetree.cb | |
| parent | d2b9ec13622d34714b4ecf8b9daf53b32665d3d7 (diff) | |
| download | coreboot-81dd52b7eb663c6098de5d8c7c56ed572c91b539.tar.xz | |
intel/i945: Factor out ram init time stamps
Instead of having the code for the RAM init time stamps in each
mainboard’s `romstage.c`, factor it out to the northbridge code, done in
commit 771328f7 (intel/i945: add timestamps in romstage).
Change-Id: Ibb699a1fea2f0b1f3c6564d401542d2fb3249f5a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17994
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/d945gclf/devicetree.cb')
0 files changed, 0 insertions, 0 deletions