preliminary Intel D945GCLF Atom+i945 support.

ram init fails, as the i945 driver currently only supports the mobile version
of the chipset..

Not sure how much sense it makes to check this in, but since it's a nice and
cheap board, maybe someone wants to work on this.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 167 insertions, 0 deletions

diff --git a/src/mainboard/intel/d945gclf/fadt.c b/src/mainboard/intel/d945gclf/fadt.c
new file mode 100644
index 0000000000..72d94332ef
--- /dev/null
+++ b/src/mainboard/intel/d945gclf/fadt.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+ 	header->length = sizeof(acpi_fadt_t);
+ 	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+  	fadt->sci_int = 0x9;
+ 	fadt->smi_cmd = APM_CNT;
+ 	fadt->acpi_enable = ACPI_ENABLE;
+ 	fadt->acpi_disable = ACPI_DISABLE;
+  	fadt->s4bios_req = 0x0;
+ 	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+	fadt->pm2_cnt_len = 2;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+ 	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 85;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = 0x03;
+
+ 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ 	fadt->reset_reg.space_id = 0;
+ 	fadt->reset_reg.bit_width = 0;
+ 	fadt->reset_reg.bit_offset = 0;
+ 	fadt->reset_reg.resv = 0;
+ 	fadt->reset_reg.addrl = 0x0;
+ 	fadt->reset_reg.addrh = 0x0;
+
+ 	fadt->reset_value = 0;
+ 	fadt->x_firmware_ctl_l = (unsigned long)facs;
+ 	fadt->x_firmware_ctl_h = 0;
+ 	fadt->x_dsdt_l = (unsigned long)dsdt;
+ 	fadt->x_dsdt_h = 0;
+
+ 	fadt->x_pm1a_evt_blk.space_id = 1;
+ 	fadt->x_pm1a_evt_blk.bit_width = 32;
+ 	fadt->x_pm1a_evt_blk.bit_offset = 0;
+ 	fadt->x_pm1a_evt_blk.resv = 0;
+ 	fadt->x_pm1a_evt_blk.addrl = pmbase;
+ 	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1b_evt_blk.space_id = 1;
+ 	fadt->x_pm1b_evt_blk.bit_width = 0;
+ 	fadt->x_pm1b_evt_blk.bit_offset = 0;
+ 	fadt->x_pm1b_evt_blk.resv = 0;
+ 	fadt->x_pm1b_evt_blk.addrl = 0x0;
+ 	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1a_cnt_blk.space_id = 1;
+ 	fadt->x_pm1a_cnt_blk.bit_width = 16;
+ 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm1a_cnt_blk.resv = 0;
+ 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1b_cnt_blk.space_id = 1;
+ 	fadt->x_pm1b_cnt_blk.bit_width = 0;
+ 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm1b_cnt_blk.resv = 0;
+ 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm2_cnt_blk.space_id = 1;
+ 	fadt->x_pm2_cnt_blk.bit_width = 8;
+ 	fadt->x_pm2_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm2_cnt_blk.resv = 0;
+ 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ 	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm_tmr_blk.space_id = 1;
+ 	fadt->x_pm_tmr_blk.bit_width = 32;
+ 	fadt->x_pm_tmr_blk.bit_offset = 0;
+ 	fadt->x_pm_tmr_blk.resv = 0;
+ 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ 	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ 	fadt->x_gpe0_blk.space_id = 1;
+ 	fadt->x_gpe0_blk.bit_width = 64;
+ 	fadt->x_gpe0_blk.bit_offset = 0;
+ 	fadt->x_gpe0_blk.resv = 0;
+ 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ 	fadt->x_gpe0_blk.addrh = 0x0;
+
+ 	fadt->x_gpe1_blk.space_id = 1;
+ 	fadt->x_gpe1_blk.bit_width = 0;
+ 	fadt->x_gpe1_blk.bit_offset = 0;
+ 	fadt->x_gpe1_blk.resv = 0;
+ 	fadt->x_gpe1_blk.addrl = 0x0;
+ 	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}