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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-23 10:07:16 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-24 10:40:40 +0000
commit346d201d73d51ae0a037f64b1bc6d530745b5d4a (patch)
treea6409d052902e76c4a87a9e34837c18a945fccb9 /src/mainboard/intel/d945gclf
parentcf32fd172928467ac5bbd4fb372b71230c81cf12 (diff)
downloadcoreboot-346d201d73d51ae0a037f64b1bc6d530745b5d4a.tar.xz
nb/intel/i945: Use DEBUG_RAM_SETUP
Avoid preprocessor here, also we never set loglevel to value of >8 so the call would not be made. The calls to ram_check() were removed, for a long time that function has not tested start..stop region. Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 18a772171d..6cb24a6786 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -151,9 +151,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
- dump_spd_registers();
-#endif
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);