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authorArthur Heymans <arthur@aheymans.xyz>2019-10-04 13:59:29 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-11 12:21:25 +0000
commit2437fe9dfab8e4056b633a39d51d07aa81ab3c9d (patch)
tree1dd071659a48c99c1e71ddf03b8cdf416da324c2 /src/mainboard/intel/d945gclf
parentcbe5357de02fa9f25ab9c0ca557e3057c701b059 (diff)
downloadcoreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.tar.xz
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c26
1 files changed, 1 insertions, 25 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index bad2b6d538..f6fc8df2f4 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -89,31 +89,7 @@ static void early_ich7_init(void)
reg32 |= (1 << 31) | (1 << 27);
pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
- RCBA32(0x0088) = 0x0011d000;
- RCBA16(0x01fc) = 0x060f;
- RCBA32(0x01f4) = 0x86000040;
- RCBA32(0x0214) = 0x10030549;
- RCBA32(0x0218) = 0x00020504;
- RCBA8(0x0220) = 0xc5;
- reg32 = RCBA32(0x3410);
- reg32 |= (1 << 6);
- RCBA32(0x3410) = reg32;
- reg32 = RCBA32(0x3430);
- reg32 &= ~(3 << 0);
- reg32 |= (1 << 0);
- RCBA32(0x3430) = reg32;
- RCBA16(0x0200) = 0x2008;
- RCBA8(0x2027) = 0x0d;
- RCBA16(0x3e08) |= (1 << 7);
- RCBA16(0x3e48) |= (1 << 7);
- RCBA32(0x3e0e) |= (1 << 7);
- RCBA32(0x3e4e) |= (1 << 7);
-
- // next step only on ich7m b0 and later:
- reg32 = RCBA32(0x2034);
- reg32 &= ~(0x0f << 16);
- reg32 |= (5 << 16);
- RCBA32(0x2034) = reg32;
+ ich7_setup_cir();
}
void mainboard_romstage_entry(void)